The 31st edition of the IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2024), set against the stunning backdrop of Marina Bay Sands Convention Center in the heart of Singapore.
15-18th July 2024
Marina Bay Sands Expo and Convention Centre, Singapore
Ladies and gentlemen, distinguished guests, and esteemed colleagues, a warm greeting to the 31st edition of the IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2024), set against the stunning backdrop of Marina Bay Sands Convention Center in the heart of Singapore! As we embark on this next chapter of the IPFA legacy, we find ourselves in a city synonymous with innovation and technological marvels. Singapore’s iconic skyline mirrors the heights of excellence we aim to achieve in our exploration of the physical and failure analysis of integrated circuits. This symposium remains dedicated to fostering collaboration and knowledge exchange among the brightest minds in the field. The discussions and insights shared here will undoubtedly contribute to the ever-evolving landscape of integrated circuit analysis and design.
In addition, for the first time, IPFA will be co-located with the International ESD Workshop (IEW-Asia 2024). This is a unique opportunity for both communities to reach out to a wider audience! Prospective authors and attendees may visit the IEW-Asia 2024 website.
We are looking forward to welcoming you to a memorable experience!
Highlights from 2023
Our Location
Keynote Speakers
Dr. Julien Ryckaert, imec, Belgium
Compute scaling beyond the finFET era: the road to CMOS 2.0
Dr. Yeo Yee-Chia, Agency for Science, Technology, and Research (A*STAR), Singapore
Enabling Next-Generation Heterogeneously Integrated Computing Systems Incorporating Photonics
Tutorial Speakers
Dr. Jim Vickers, Thermofisher Scientific, USA
Three decades of IC-Probing Technology: The Great Loop from E-beam Methods to Optical Methods and back to E-beam Methods
Dr. Michael Khazhinsky, Silicon Labs, USA
ESD and Latch-up Design Verification. How Electronic Design Automation (EDA) Helps to Avoid and Solve Product Problems
Dr. Yan Li, Samsung Semiconductor Inc., USA
Advanced Packaging technologies for chiplet and memory integration
Dr. Sebastian Brand, Fraunhofer IWMS, Germany
Exploring High-Resolution Non-Destructive Defect Localization and Signal Processing Advances in Microelectronics Failure Analysis
Professor Cristian Zambelli, University of Ferrara, Italy
A cross-layer assessment of Emerging memories reliability
Professor Fei Hui, Zhengzhou University, China
Reliability study of 2D material and its-based memory devices for future technology nodes
Professor Michel Bosman, National University of Singapore, Singapore
The relevance of Aberration-Corrected STEM for IC Failure Analysis
Professor Enrico Zanoni, University of Padova, Italy
GaN devices, technology, characterization, reliability challenges and future prospects
Invited Speakers
Dr. Michael Khazhinsky, Silicon Labs, USA
ESD and Latch-up Design Verification Challenges in Packaged Parts and Modules
Dr. Sebastian Brand, Fraunhofer IWMS, Germany
Advances in high-resolution non-destructive defect detection and localization enhanced by intelligent signal processing
Dr. Shahin Tajik, Worcester Polytechnic Institute, USA
Securing Hardware against Physical Adversaries with Unlimited Resources
Dr. Yan Li, Samsung Semiconductor Inc., USA
The Applications of Simulation and Artificial Intelligence in Advanced Packaging
Professor Fei Hui, Zhengzhou University, China
In-situ observation of reliable nanosynpatic response in low-dimensional materials using CAFM
Jayant D’Souza, Siemens, USA
Increasing chain diagnosis resolution in the age of backside power
Professor Enrico Zanoni, University of Padova, Italy
Mechanisms of charge capture and emission in power GaN HEMTs
Professor Cristian Zambelli, University of Ferrara, Italy
3D NAND Flash memories reliability: a cross-layer perspective
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